The present invention relates to a semiconductor integrated circuit device and, more particularly, the invention relates to a technique which is effective for use in a semiconductor memory device having a large storage capacity and which is required to achieve high-speed reading of data.
It was found by a search conducted after the present invention was made that there are the following publications disclosing techniques which seem to be related to the present invention: Japanese Unexamined Patent Publication No. Hei 10(1998)-340579 (corresponding to U.S. Pat. No. 5,881,009, called publication 1 below), Japanese Unexamined Patent Publication No. Hei 11(1999)-39871 (corresponding to U.S. Pat. No. 5,881,017, called publication 2 below), Japanese Unexamined Patent Publication No. Hei 10(1998)-334659 (corresponding to U.S. Pat. No. 5,892,730, called publication 3 below), Japanese Unexamined Patent Publication No. Hei 9(1997)-198873 (corresponding to U.S. Pat. No. 5,825,709, called publication 4 below), Japanese Unexamined Patent Publication No. Hei 7(1995)-282583 (hereinbelow, called publication 5), Japanese Unexamined Patent Publication No. Hei 4(1992)-162286 (corresponding to U.S. Pat. No. 5,289,413, hereinbelow, called prior art 6), Japanese Unexamined Patent Publication No. Hei 7(1995)-272479 (corresponding to U.S. Pat. No. 5,572,477, hereinbelow, called publication 7), Japanese Unexamined Patent Publication No. Hei 7(1995)-272481 (hereinbelow, called publication 8), and Japanese Unexamined Patent Publication No. Hei 11(1999)-16361 (hereinbelow, called publication 9).
In relation to the present invention, the publications 1 to 9 will be briefly described as follows. In the technique disclosed in publication 1, when even-numbered data is outputted first, an operation timing of an odd-numbered data bus amplifier and that of an even-numbered data bus amplifier are made asynchronous with each other. In the techniques disclosed in publications 2 and 3, the operation timing of a read buffer at the ante-stage of a read register is pipeline operated on a unit basis. In the technique of publication 4, the operation timing of a sense amplifier at the ante-stage of an output latch is shifted according to the column. In the technique of publication 5, the operation timing of a sense amplifier at the ante-stage of an output latch is shifted. In the technique of publication 6, amplifiers at the ante-stage of output latches are alternately operated. In the technique of publication 7, the operation timing of a column switch at the ante-stage of an output latch is pipeline operated. In the technique of publication 8, the operation timing of a data detecting circuit at the ante-stage of an output latch is shifted according to an address. In the technique of publication 9, the driving capabilities of sense amplifiers at the ante-stage of latches are made various. In the publications 1 to 9, there is no description suggesting the necessity of realizing an increase in speed of a prefetch operation by a simple configuration, as is provided in the present invention described hereinlater.
A DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) inputs/outputs data at both edges of a clock. When the DDR SDRAM operates at a clock frequency of 200 MHz, a data transfer rate of 400 Mbps which is double is achieved. When a chip having a configuration similar to that of an SDRAM has the DDR, the inside of the chip has to operate at a double frequency. This, however, cannot be realized by the same device. In the DDR SDRAM, the operation frequency in the chip is set to be equal to that of the SDRAM by a prefetch operation, and only the speed of the input/output of data is increased to realize 400 Mbps. The DDR SDRAM has a data transfer system from a main amplifier to an output buffer, which is largely different from that in the SDRAM.
In the SDRAM, about 20% of a current consumption ICC is considered to be charging/discharging currents of global input/output lines GIO as data transfer lines extending from the main amplifier to the output buffer. Consequently, when a prefetch operation is performed, the peak current becomes an issue. To be specific, when data is input/output on a 16-bit unit basis, 32 main amplifiers and 32 global input/output lines GIO which are double those provided in the SDRAM operate simultaneously in a 2N prefetch operation, and 64 main amplifiers and 64 global input/output lines GIO, which are four times as many as those in a 4N prefetch operation. The peak current is therefore an important issue. When a method of increasing the speed of the main amplification circuit and the global input/output line GIO is employed in order to improve the performance, a problem occurs in that the peak current further increases.
An object of the invention is to provide a semiconductor integrated circuit device comprising a signal transmission circuit having an increased data input/output speed and an improved operation margin with a simple configuration. Another object of the invention is to provide a semiconductor integrated circuit device comprising a semiconductor storage having, in addition to an increased processing speed and an improved operation margin, a reduced area and a reduced power consumption. The above and other objects of the invention and novel features will become apparent from the description in this specification and from the appended drawings.
The outline of a representative aspect of the invention disclosed in the application will be described as follows. First and second data is transferred in parallel through a first signal transmission path, amplified by first and second relay amplification circuits, and transmitted via a second signal transmission path to first and second output registers, and an output circuit for serially outputting the first and second data held by the first and second output registers, respectively, on the basis of address information is provided. In the first and second relay amplification circuits, with respect to one, to be outputted first, of the first and second data, an output timing of the other data to be outputted later to the second signal transmission path is delayed.
The outline of another representative aspect of the invention disclosed in the application will be described as follows. First and second data is transferred in parallel through a first signal transmission path, amplified by first and second relay amplification circuits, and transmitted via a second signal transmission path to first and second output registers, and an output circuit for serially outputting the first and second data held by the first and second output registers, respectively, on the basis of address information is provided. A selection circuit is provided for each of the first and second relay amplification circuits to make one, to be outputted first, of the first and second data correspond to the first output register and to make the other data to be outputted later correspond to the second output register, and the transfer rate of the second signal transmission path corresponding to the first output register is set to be higher than that of the second signal transmission path corresponding to the second output register.